(1) Field of the Invention
This invention relates to semiconductor integrated circuits, and more particularly, to a method for fabricating totally self-aligned contacts on integrated circuits, and more specifically on dynamic random access memory circuits.
(2) Description of the Prior Art
There is a continuing effort in the semiconductor industry to increase the circuit density on semiconductor chips to improve the performance and reduce the cost. The increase in performance is partly due to improved high resolution optical lithography and the directional etching achieved in plasma etchers. Another method of increasing the device density on a chip in conjunction with the improved lithography and plasma etching is to employ self-aligning techniques that reduce the alignment tolerance during mask alignment on the chip.
The dynamic random access memory (DRAM) circuit is one type of integrated circuit chip that is experiencing this increase in circuit density. The DRAM chip is composed, in part, of an array of memory cells. Each cell is formed from a single pass transistor, typically a field effect transistor (FET), and a storage capacitor. The storage capacitor makes contact to one of the two source/drain areas of the FET and a bit line makes contact to the other source/drain area of each of the transistors. The number of memory cells on the DRAM chip are expected to reach 1 Gigabits while the minimum feature sizes within the cell are expected to be less than 0.20 micrometers (um) by the year 2001, as projected by the Semiconductor Industry Association's technology roadmap as reviewed in the article "Processes of the Future", Solid State Technology, pages 42-54, February 1995.
If these goals are to be achieved, the DRAM cell must be further reduced in size, and the bit line and node contacts to the FET source/drain areas on the substrate must also be correspondingly reduced in size and have a more accurately alignment tolerances. To better understand the nature of the problem in reducing the cell size, a typical prior art DRAM cell partially completed is shown schematically in elevational view in FIG. 1, and described in detail. Cross sections through the cell area are also shown in FIGS. 2 and 3. The partially completed DRAM cell structure in FIG. 1 is shown having a bit line contact 1 that is common to two adjacent capacitor node contacts 5 with gate electrodes 16 between the bit line contacts and node contacts.
Starting with FIG. 1, the typical prior art DRAM cells are formed on a semiconductor substrate 10, usually composed of a P.sup.- doped single crystalline silicon. A relatively thick Field OXide (FOX) 12 is formed on and in portions of the substrate surface surrounding and electrically isolating active devices areas 7, as shown in FIG. 1. The field oxide 12 is usually formed by the LOCal Oxidation of Silicon (LOCOS) method commonly practiced in the semiconductor industry. The LOCOS process consists of depositing or thermally growing a thin pad oxide composed of silicon oxide on the substrate surface and then depositing a silicon nitride (Si.sub.3 N.sub.4) layer, usually by chemical vapor deposition (CVD), the nitride layer serving as a barrier to thermal oxidation. The silicon nitride layer is patterned leaving portions over the silicon substrate where active device regions are required semiconductor devices, such as field effect transistors. The silicon substrate is then subjected to an oxidizing ambient, such as steam oxidation, to form the relatively thick field oxide regions 12 composed of silicon oxide (SiO.sub.2) surrounding the active device areas 7. A portion of the field oxide also naturally forms under the perimeter of the nitride layer by the lateral oxidation of the silicon substrate and is commonly referred to, in the industry, as the "bird's beak" because of its shape. After removing the silicon nitride layer, for example in a hot phosphoric acid solution, and the pad oxide in a dilute solution of hydrofluoric acid (HF), a FET gate oxide is formed on the device areas 7 using a thermal oxidation. Polysilicon gate electrodes 16 and the interconnecting word lines 16' are then formed by patterning a polysilicon layer, as shown in FIG. 1. The gate electrodes 16 and word lines are usually heavily doped with an N type electrically conductive dopant, such as phosphorus (P) or arsenic (As) to provide low resistance. It is also common practice in the semiconductor industry to provide a first insulating layer (not shown in FIG. 1) over the gate electrodes and word lines, that is usually patterned at the same time as the electrodes and word lines. This first insulating layer or oxide cap layer serves as an etch stop layer when the self-aligned contacts that extend over the gate electrodes are etched in a second insulating layer. After forming the gate electrodes 16, lightly N-type doped source/drain regions are formed in the active device areas 7, for example by ion implantation, adjacent to the gate electrodes 16, and then a blanket sidewall insulating layer is deposited and anisotropically etched back forming sidewall spacers 18 on the sidewalls of the gate electrodes 16. This essentially completes the field effect transistors (FETs). A second insulating layer 20 is blanket deposited over the substrate surface, and contact openings are etched in layer 20 to the source/drain regions to form the bit line contacts 1. If the node contacts and storage capacitors are to be formed first, then the node contacts 5 are etched to the source/drain areas, also as depicted in FIG. 1. The cross section 3-3' through the node contact 5 in FIG. 1 is shown in cross sectional view in FIG. 3. Also shown in FIG. 3 is the gate oxide 14 under the gate electrode 16, the LDD source/drain areas 15 adjacent to the gate electrode, and the heavily doped source/drain area 17. If the bit line contact 1 is etched first, then the cross section 2-2' through the bit contact 1 region in FIG. 1 is as shown in cross sectional view in FIG. 2. The gate oxide 14, LDD regions 15 and source /drain area 17 are also depicted, as shown in FIGS. 3. The contact openings 1 and 5, are formed by anisotropic etching using a patterned photoresist layer 22 etching mask, as shown in FIG. 2 and 3. As is commonly practiced in the semiconductor industry the contact openings are etched in layer 20 to the cap oxide 19 over the gate electrodes 16 so as to provide a self-aligned contact to the gate electrode adjacent to the sidewalls 18. The width W of the contact openings in photoresist masking layer 20 are aligned within the active device areas 7 having an alignment spacing L sufficient to prevent the contact from partially or completely lying outside the active device area 7, as shown in FIG. 1.
Unfortunately, a number of process limitations occur when the active device area is reduced in size to provide for the increase in DRAM cell density. To provide reliable memory cells having repeatable electrical characteristics it is necessary that the node or bit line contacts 1 and 5 lie completely within the source/drain areas (active device areas 7 in FIG. 1). However, because of the resolution limitations of the lithography there is an increased risk factor that the contacts will lie outside the source/drain area. For example, the current lithographic limitations on feature size is about 0.4 micrometers (um), and the alignment tolerance is about 0.2 um. Therefore, if the width W of the active device areas 7 in FIG. 1 is reduced from 1.0 um to 0.6 um to improve the cell pitch, and the alignment tolerance L (in FIG. 1) is maintained at a value of at least 0.2 um the width D of the contact openings 1 or 5 would have to be only about 0.2 um in width which is less than the lithographic resolution limits. On the other hand, if the contact width D is sufficiently large (0.4 nm) to satisfy the lithograph resolution limits, then the alignment tolerance (about 0.1 um) is insufficient for the contacts to lie completely within the active device area. The width of the device area W is also limited to a value of at least 0.6 um in order to provide a sufficient wide FET channel length to provide the required current driving capability for the pass transistor (FET).
Therefore there is still a strong need in the semiconductor industry for making reliable DRAM circuits with reduced cell size by methods that extend the current lithographic limits.